The present invention relates to a successive approximation analog/digital (hereinafter referred to as "A/D") converter that converts an analog input voltage to a digital value for output and in particular, it relates to such a successive approximation A/D converter which is capable of achieving a reduction in power consumption.
FIG. 2 and 3 show a successive approximation A/D converter in the prior art, with FIG. 2 presenting a schematic block diagram of the converter and FIG. 3 presenting a diagram of an operating waveform thereof.
The A/D converter in FIG. 2 is provided with a comparator 1 that compares an analog input voltage VI to be converted and a reference voltage VR. The analog input voltage VI is input to a + input terminal of the comparator 1. A referencing result signal RE output from the output side of the comparator 1 is input to a conversion control unit 2. The conversion control unit 2 provides control for causing the reference voltage VR to change successively for comparison against the analog input voltage VI and for converting the analog input voltage VI to a digital value, and is provided with a conversion start signal ST which issues a conversion-start instruction in specific cycles and a clock signal CK that constitutes a basis for the operation. The input side of a successive conversion register 3 is connected to the output side of the conversion control unit 2.
The successive conversion register 3 may be a register that holds, for instance, 5-bit data and, in compliance with control provided by the conversion control unit 2, sequentially updates the data from the most significant bit (hereinafter referred to as "MSB") to the least significant bit (hereinafter referred to as "LSB") for output. The input side of a 5-bit digital/analog (hereinafter referred to as "D/A") conversion unit 4 is connected to the output side of the successive conversion register 3. The D/A conversion unit 4 generates a voltage that corresponds to a 5-bit digital input value and outputs it as a reference voltage VR. The output side of this D/A conversion unit 4 is connected to a-input terminal of the comparator 1. In addition, an output unit 5 for holding the final 5-bit value as a digital output signal DO indicating the conversion results for output, is connected to the output side of the successive conversion register 3.
Next, the operation of the A/D converter in the prior art shown in FIG. 2 is explained.
It is assumed that this A/D converter is capable of converting analog input voltages VI ranging from 0 V through 3.1 V in increments of 0.1 V and that 2.3 V is input as the analog input voltage VI.
When the conversion start signal ST and the clock signal CK are provided at the point in time t1 in FIG. 3, processing starts in the conversion control unit 2, and "1" is set as the MSB at the successive conversion register 3 by a conversion control signal CV provided by the conversion control unit 2 with the timing of the clock signal CK at the following point in time t2. In other words, the value of the output signal from the successive conversion register 3 is set to "10000". The output signal from the successive conversion register 3 is provided to the D/A conversion unit 4, and the reference voltage VR1 at the output side of the D/A conversion unit 4 is set to 1.6 V. The analog input voltage VI and the reference voltage VR1 are compared at the comparator 1, and the referencing result signal RE (VI&gt;VR1) is communicated to the conversion control unit 2. With this, while holding the MSB at "1", the conversion control unit 2 sets the next bit (the fourth bit) to "1".
The value of the output signal from the successive conversion register 3 is changed to "11000" by the conversion control signal CV provided by the conversion control unit 2, with the timing of the clock signal CK at the point in time t3. The output signal from the successive conversion register 3 is provided to the D/A converter 4, and the reference voltage VR2 at the output side of the D/A converter 4 is set to 2.4 V (=1.6 V+0.8 V). The analog input voltage VI and the reference voltage VR2 are compared to each other at the comparator 1 and the resulting referencing result signal RE (VI&lt;VR2) is communicated to the conversion control unit 2. With this, while holding the MSB at "1", the conversion control unit 2 sets the next bit (the fourth bit) to "0" and also sets the subsequent bit (the third bit) to "1".
The value of the output signal from the successive conversion register 3 is changed to "10100" by the conversion control signal CV provided by the conversion control unit 2 with the timing of the clock signal CK at the point in time t4. The output signal from the successive conversion register 3 is provided to the D/A converter 4, and the reference voltage VR3 at the output side of the D/A converter 4 is set to 2.0 V (=1.6 V+0.4 V). The analog input voltage VI and the reference voltage VR3 are compared to each other at the comparator 1 and the referencing result signal RE (VI&gt;VR3) is communicated to the conversion control unit 2. With this, while holding the MSB at "1", the fourth bit at "0", and the third bit at "1", the conversion control unit 2 sets the subsequent bit (the second bit) to "1".
Likewise, the value of the output signal from the successive conversion register 3 is changed to "10110" at the point in time t5, and the reference voltage VR4 at the output side of the D/A converter 4 is set to 2.2 V (=1.6 V+0.4 V+0.2 V). The analog input voltage VI and the reference voltage VR4 are compared to each other at the comparator 1 and the referencing result signal RE (VI&gt;VR4) is communicated to the conversion control unit 2. With this, while holding the MSB at "1", the fourth bit at "0", the third bit at "1", and the second bit at "1", the conversion control unit 2 sets the LSB to "1".
The value of the output signal from the successive conversion register 3 is changed to "10111" at the point in time t6, and the reference voltage VR5 at the output side of the D/A converter 4 is set to 2.3 V (=1.6 V+0.4 V+0.2 V+0.1 V).
The analog input voltage VI and the reference voltage VR5 are compared to each other at the comparator 1 and the referencing result signal RE (VI=VR5) is communicated to the conversion control unit 2. With this, while holding the MSB at "1", the fourth bit at "0", the third bit at "1", the second bit at "1", and the LSB at "1", the conversion control unit 2 provides a latch signal LA to the output unit 5 where the digital output from the successive conversion register 3 is held. The output unit 5 then outputs the conversion result as the digital output signal DO.
Then, with the next conversion start signal ST, successive conversion of a new analog input voltage VI is started.
However, A/D converters in the prior art are started up to perform the conversion operation by a conversion start signal ST, which is provided in specific cycles, and since the analog input voltage VI is input only intermittently, a state of no signal is maintained for much of the time and the conversion operation is sustained even during periods of time when the conversion operation is not required. Thus, power is consumed wastefully through the operating currents at the circuits involved in the conversion.